AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.4.1.2. Plan for On-Chip Debugging

The Intel® Quartus® Prime software includes on-chip debugging tools that offer different advantages and trade-offs, depending on the system, design, and user.

Evaluate on-chip debugging options early in the design process to ensure that your system board, Intel® Quartus® Prime project, and design files are all set-up to support the appropriate options.

Timing errors due to unspecified timing requirements can appear as functional failures of the design. If you are able locate the functional block where errors originate, it is easier to find the source of the errors.

For more information about in-system design debugging, as well as the Intel® Quartus® Prime debugging tools, refer to Intel® Quartus® Prime Pro Edition User Guide: Debug Tools.

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