AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.6.4.1. Check CDC Design Assistant Rule Violations

The Intel® Quartus® Prime software Design Assistant uses design rule checks (DRC) to identify potential issues on signals or buses that are crossing clock domains.

Click Compilation Report > Timing Analyzer > Design Assistant (Signoff) > Results to view the CDC report.

Figure 10. Design Assistant CDC DRCs

The top section of the figure shows the list of CDC rules that Design Assistant verifies. The bottom section provides a description and recommendation for the rule violation.

Refer to Design Assistant Design Rule Checking in Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

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