AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.4.1.1. Plan for the Target FPGA Device

The devices in each Intel FPGA family are available with different design densities, speed grades, and packaging options to accommodate different applications. in design planning, choose a device with a specification that meets your timing requirements.

Some FPGA device feature requirements to consider are:

  • Performance
  • Logic and memory density
  • I/O density
  • Power utilization
  • Packaging
  • Cost

The Intel® Quartus® Prime software optimizes and analyzes your design using different timing models for each speed grade. If you migrate to a device with a different speed grade, you must perform timing analysis again to ensure that there are no timing violations due to changes in the device speed grade.

For more information about choosing a device, refer to Design Planning in Intel® Quartus® Prime Pro Edition User Guide: Getting Started.

To quickly find and compare the specifications and features of Intel FPGA devices and development kits, refer to the Product Selector tool on the Intel website.

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