AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.4.1. Timing Closure Planning at Specification Stage

Start planning for timing closure at the specification stage and decide how you would like to interface with the device in the target system before coding for the design blocks.

Create a block diagram that shows partitioning of the desired functionality into specific blocks. There is no limit to how big or small a block can be.

Very small design blocks might be difficult to track, while very large design blocks can be difficult to debug. Try creating blocks that encapsulate distinct functionality. Keep blocks to a size that is convenient for debugging during functional simulation and timing closure.

Refer to the following topics for timing closure planning at the specification stage:

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