AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents

1.6.2. Improper Timing Constraints

The Compiler attempts to optimize your design according to the constraints that you provide. Therefore, improper or missing timing constraints can contribute to timing failure. The Timing Analyzer does not analyze unconstrained paths. You must review the Timing Analyzer report to ensure you have constrained all required timing paths.

If you omit some of the required constraints, the Timing Analyzer may generate a report without any violations. However, if the missing constraints are critical, then your design implementation may not perform as intended. Therefore, you must fully constrain your design.

In addition to missing timing constraints, another common cause of timing closure issues is under-specification or over-specification of timing constraints.

You must analyze your timing analysis report for all false or multi-cycle paths. The Timing Analyzer attempts to optimize all paths as valid, single-cycle paths, unless you identify them as false or multi-cycle paths. This might cause valid paths to fail timing requirements (depending on which paths the Fitter optimizes first). To avoid this scenario, identify false and multi-cycle paths in the .sdc file.

When you specify aggressive timing constraints on one domain, the Timing Analyzer attempts to optimize that domain earlier than other clock domains. You can use this technique to selectively apply more optimization effort to only one domain. The benefit you derive from this is design dependent. Also, you must manually analyze the failing paths to determine if they have met your requirements, even if the paths failed the over-constrained requirement. In general, use real requirements for constraining your design.

The Timing Analyzer assumes all clocks in a design are related, and checks for all possible paths in the design. Apply false path constraints between clock domains that do not have valid paths.

You can over-constrain the design if you want to improve timing performance on select domains, particularly if compiling individual design blocks. If you can meet more stringent constraints at the block level, it can be easier to meet the timing after you integrate the blocks together. This technique compensates for delays that cannot be accurately predicted at block-level implementation.

Ensure that you target the right signals that you want to constrain. Be careful in use of wild card characters in defining timing constraints. You can unknowingly constrain unexpected targets, leading to constraints on the wrong paths, or could lead to getting false positive timing results.

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