AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents Check Constraint Diagnostics

The Timing Analyzer can generate a set of diagnostic reports that help check timing constraints.

Click Tasks > Reports > Constraint Diagnostics to generate these reports.

Figure 7. Timing Analyzer Constraint Diagnostics

You can use the following commands to generate the reports to verify your constraints:

  • Report Unconstrained Paths—reports illegal or unconstrained clocks, input or output ports, and paths.
  • Report SDC—reports all SDC constraints that apply.
  • Report Ignored SDC—reports all SDC assignments that do not apply.
  • Check Timing—reports issues on critical fields like latches, loops, no clock drivers, and others.
  • Report False Path—reports all of the false paths that apply in the design.
  • Report Exceptions—reports a list all exceptions that apply in the design.
  • Report Exceptions Reachability —reports the percentage of reachability on the targets you specified in your exceptions.