AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents Plan for Verification

In general, designs that target large FPGAs are complex in nature, requiring comprehensive planning for design verification. You can use any of the supported third-party simulators to run functional verification on your design.

Plan to verify the design by exercising it with a simulation test suite at the RTL level. This level of verification ensures that the HDL contains the functionality you want, allowing you to focus on any potential timing problems.

If you have functional and timing problems simultaneously, it can be difficult to isolate issues and the correction that you need, which increases the necessary debug time.

Functional issues (such as incorrect interpretation of specifications, or implementation) may mask potential timing problems in the design, resulting in the need for engineering change orders (ECOs) at a later stage.

When using design partitions, you can verify the individual partitions. You can then reuse some of your partition-level test benches and test cases in the top-level test suite.

For more information about using third-party simulators for simulation, refer to Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation.

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