AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents Using Optimal Compiler Settings for Your Design

In addition to using the correct design methodology and proper timing constraints, use the optimal Compiler settings for your design goals.

The Intel® Quartus® Prime software offers many settings to help you meet different design requirements. If you do not specify the appropriate setting, design performance may suffer.

The Intel® Quartus® Prime software has various settings to help meet different design requirements. For example, if your design targets a mobile device, you might specify the Aggressive power setting to optimize your design for lowest power consumption. Similarly, if your design targets a low-cost system, you might pick a device with a specific architecture and optimize your design for that architecture. If you want to reduce the size of the design, you can optimize for Aggressive area.

The Compiler's default Optimization Mode settings offer a balance of performance, area, routability, power, and compilation time. By trading off one optimization for another, you can meet your preferred design requirements.

Select the Optimization Mode in Assignments > Settings > Compiler Settings > Optimization Mode.

Figure 3. Compiler Optimization Modes

There is no single collection of settings that achieves the best performance for all designs. Each design is unique, and a setting set that derives the best performance for one design has a different impact in another design.

Specifying the Superior performance optimization modes can help in some designs, but some of the modes can have a detrimental impact on your primary goal. You might be making optimizations that increase the compilation time without a corresponding improvement in performance. Only apply settings that help meet your design goals.

The settings that you specify for a project revision are specific to that revision. When you make substantial changes to a design, you may need to modify some of the Compiler settings. Whenever you make large changes in your design, you can use the Design Space Explorer II (DSE) to run seed sweeps that identify the best collections of settings for your revision. You can do multiple DSE runs with different compile settings and using multiple seeds by clicking Tools > Launch Design Space Explorer II.

Figure 4. Design Space Explorer II Exploration Options

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