AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents

1.6. Resolving Common Timing Issues

When the Timing Analyzer reports failing paths, verify if the failing requirements are correct. By default, the Timing Analyzer handles all clock domains as related, and this can cause some invalid requirements. To correct this condition, group clocks in your design appropriately. Analyze the datapath to determine how you can reduce any critical path delays.

This section contains examples of commonly encountered timing issues and troubleshooting practices:

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