AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.6.6. Small Margin Timing Constraint Failures

If your design fails to meet timing requirements by a small margin, you can use DSE II to help you select the optimum project settings to meet timing. DSE II runs multiple compilations and compares the results to determine the best combination of settings. Using DSE II to run a seed sweep also helps you compensate for the seed effect, as Change Fitter Placement Seeds describes.

If you make changes to your RTL code or project settings, run a DSE II seed sweep to ensure that the RTL or settings changes are the true cause of improvements, rather than the seed effect.

If your design still fails to meet timing by a small margin, you can use the best performing seed to lock down the placement of clocks, RAMs, and DSPs from that compilation. You lock these placements through assignment back-annotation, and then run another round of seed-sweep using the locked-down placements. The subsequent compilations can benefit from the initial, desired placement settings of the previous best performing seed.

To lock down placement through assignment back-annotation, click Assignments > Back-Annotate Assignments, and then select the types of assignments to back-annotate. You can choose to append the back-annotated assignments to the .qsf, or to create a Tcl file of assignments that you can source to the .qsf.

Figure 12. Back-Annotate Assignments Dialog Box

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