AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents
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The Timing Analyzer generates a report on the MTBF of signals crossing clock domains. The Timing Analyzer can also generate a summary list of all the signals, buses, and resets that cross clock domains.

You can generate the summary list by clicking Tasks > Reports > Clock Domain Crossings in the Timing Analyzer.

Figure 11. Report Asynchronous CDC Full Report