AN 584: Timing Closure Methodology for Advanced FPGA Designs
ID
683145
Date
10/08/2021
Public
1.1. Plan Early for Timing Closure
1.2. Customize Settings Per Application
1.3. Change Fitter Placement Seeds
1.4. Planning for Timing Closure
1.5. Best Practices for Timing Closure
1.6. Resolving Common Timing Issues
1.7. Conclusion
1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.2. Customize Settings Per Application
You must consider a variety of features before choosing a device or a specific technology for your applications. For example, factors such as device cost, operating speed, and power are some key points for consideration early in your system design.
The Intel® Quartus® Prime software includes many precise settings that help you to achieve your specific design goals. The default settings generally provide the most balanced performance, power, and resource optimization trade-offs, but you can choose non-default settings to tailor the implementation for your application.