Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card
ID
683129
Date
7/20/2020
Public
1. About this Document
2. Introduction
3. Getting Started with Platform Configuration
4. The Accelerator Functional Unit (AFU)
5. Developing AFUs with the OPAE SDK
6. AFU In-System Debug
7. Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card Archives
8. Document Revision History for Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card
5.3.2.1. Specify the Platform Configuration
5.3.2.2. Design the AFU
5.3.2.3. AFU Design Guidelines
5.3.2.4. Partial Reconfiguration Design Guidelines
5.3.2.5. Specify the Build Configuration
5.3.2.6. Generate the ASE Build Environment
5.3.2.7. Verify the AFU with ASE
5.3.2.8. Generate the AF Build Environment
5.3.2.9. Generate the AF
5.3.2.1.1. Specify the AFU's UUID
5.3.2.1.2. Request a Top-level Interface
5.3.2.1.3. Extend a Top-level Interface
5.3.2.1.4. Request Device Interface Pipelining
5.3.2.1.5. Request Device Interface Clock-crossing
5.3.2.1.6. Specify a Requested Device as Optional
5.3.2.1.7. Specify AFU User Clock Timing
6.1.1. Instrumenting the AFU Design for Signal Tap
To add Signal Tap instances and debug nodes to your AFU design, follow the procedure outlined in the Generating an AF Build Environment for Source Development section to create a development revision. Once you have created a development revision, use the Signal Tap GUI to instrument the AFU for in-system debug as you normally would. For more information, see the related documentation for Signal Tap.
The nlb_mode_0_stp sample AFU has already been instrumented with Signal Tap and the .stp file is located in the following OPAE SDK directory: $OPAE_PLATFORM_ROOT/hw/samples/nlb_mode_0_stp/hw/par/stp_basic.stp.