AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

7.1. Nios II Processor Subsystem

The Drive-On-Chip Design Example Nios II processor subsystem offers a fully functional processor system with debugging capabilities:

The Nios II processor subsystem comprises the following Qsys components:

  • Nios II fast processor
  • Floating-point hardware custom instructions (optional)
  • Tightly-coupled instruction and data memory
  • JTAG master
  • Performance counters
  • DDR controller
  • MOSFET gate driver SPI
  • JTAG UART
  • System console debugging RAM
  • Debugging dump memory

The ISR uses the tightly-coupled memory blocks for code and data to ensure fast predictable execution time for the motor control algorithm.

The Nios II subsystem uses the JTAG master and debug memories to allow real-time interactions between System Console and the processor. The design uses the System Console debugging RAM to send commands and receive status information. The debugging dump memory stores trace data that you can display as time graphs in System Console.

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