GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
3.1. IP Overview
The GTS PMA/FEC Direct PHY IP is for use in proprietary protocol configurations. The GTS PMA/FEC Direct PHY IP enables access to the PMA Direct, FEC Direct, and PCS Direct modes. Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for the protocol IPs that support dual simplex mode and the implementation flow.
The PMA Direct mode bypasses the FEC, PCS, and MAC Hard IP blocks. You can configure the PMA interface and core interface FIFOs in the datapath into various modes, including elastic and phase compensation modes.
The FEC Direct mode bypasses the MAC and PCS Hard IP blocks. In this mode, the PMA interface and core interface FIFOs in the datapath are set to elastic and phase compensation modes, respectively.
The PCS Direct mode bypasses the MAC Hard IP blocks. In this mode, the PMA interface and core interface FIFOs in the datapath are set to elastic and phase compensation modes, respectively.
You can use the PMA/FEC Direct PHY IP to configure the datapath into the PMA direct, PCS direct and FEC direct modes. The top-level file that generates with the IP instance includes all the available ports for your configuration. Use these ports to connect the GTS PMA/FEC Direct PHY IP to other IP cores in your design, such as GTS System PLL Clock IP, GTS Reset Sequencer IP, TX and RX serial data pins, data generator and data checker soft IP.
In PCS Direct mode, the PCS block receives the parallel data from the FPGA fabric. The PCS block is clocked by the GTS System PLL Clock IP. In FEC direct mode, FEC block receives the parallel data from the FPGA fabric. The FEC block is clocked by the GTS System PLL Clock IP. Additionally, you can also enable both the PCS and FEC blocks in your design.
Section Content
PMA Direct Supported Modes
FEC Direct Supported Modes
PCS Direct Supported Modes
Unsupported PMA/FEC/PCS Modes