GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
ID
848344
Date
8/04/2025
Public
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY IP
3.3. Configuring the GTS PMA/FEC Direct PHY IP
3.4. Dynamically Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. TX Datapath Options
3.3.4. RX Datapath Options
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.6. FEC Options
3.3.7. PCS Options
3.3.8. Avalon® Memory-Mapped Interface Options
3.3.9. Register Map IP-XACT Support
3.3.10. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.7.1. Clock Ports
3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2
3.7.4. PMA Fractional Mode
3.7.5. Input Reference Clock Buffer Protection
3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode)
3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode)
3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA
3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
6.1. Instantiating the GTS PMA/FEC Direct PHY IP
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design
6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design
6.6. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design
6.8. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description
6.9. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench
6.10. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit
8.3.2. Programming the Design into an Altera FPGA
8.3.3. Loading the Design to the Transceiver Toolkit
8.3.4. Creating Transceiver Links
8.3.5. Running BER Tests
8.3.6. Running Eye Viewer Tests
8.3.7. Running Link Optimization Tests
3.1.2. FEC Direct Supported Modes
The GTS PMA/FEC Direct PHY IP supports the following for FEC Direct modes:
- IEEE 802.3 BASE-R Firecode (2112, 2080) (CL 74)
- IEEE 802.3 RS (528, 514) (CL 108)
- ETC RS (528, 514)
- Only supported by the System PLL clocking mode
- Supports only the duplex operation mode
- Only supports single lane FEC, for multi-lane FEC, each lane operates independently, for example 4x10G-1
- All FEC modes support 1 Gbps to GTS transceiver maximum supported data rate of 12.5 Gbps for simulation, compilation and timing analysis
You can enable the FEC Direct mode in the IP parameter editor by turning on the Enable FEC option. The FEC Direct modes with FEC specifications are topology dependent to achieve different BER. FEC data to and from the PCS is 33 bits. On the PMA interface side, FEC data from and to the PMA interface is 33 bits wide for Firecode FEC and 40 bits for RS-FEC. For designs that include FEC, the gearbox enables automatically. The gearbox mode for Firecode FEC is 32:33 and 32:40 for RS-FEC.
Clocking Mode | FEC Mode | Double Width/ Single Width 16 | PMA Interface Width | PMA Interface FIFO (TX/RX) | Core Interface FIFO (TX/RX) |
---|---|---|---|---|---|
System PLL Clocking |
Firecode FEC (2112, 2080) CL74 | DW | 32 | Elastic/Elastic | Phase Compensation/Phase Compensation |
RS-FEC (528, 514) CL108 | DW | 32 | Elastic/Elastic | Phase Compensation/Phase Compensation | |
ETC RS-FEC (528, 514) | DW | 32 | Elastic/Elastic | Phase Compensation/Phase Compensation |
16 The Double width (DW) mode is when the Enable TX/RX double width transfer parameter in the GTS PMA/FEC Direct PHY IP GUI is enabled. When it is enabled, you can clock the FPGA core logic with a half rate clock. Single width (SW) mode is when this parameter is not enabled.