GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.1.2. FEC Direct Supported Modes

The GTS PMA/FEC Direct PHY IP supports the following for FEC Direct modes:

  • IEEE 802.3 BASE-R Firecode (2112, 2080) (CL 74)
  • IEEE 802.3 RS (528, 514) (CL 108)
  • ETC RS (528, 514)
  • Only supported by the System PLL clocking mode
  • Supports only the duplex operation mode
  • Only supports single lane FEC, for multi-lane FEC, each lane operates independently, for example 4x10G-1
  • All FEC modes support 1 Gbps to GTS transceiver maximum supported data rate of 12.5 Gbps for simulation, compilation and timing analysis

You can enable the FEC Direct mode in the IP parameter editor by turning on the Enable FEC option. The FEC Direct modes with FEC specifications are topology dependent to achieve different BER. FEC data to and from the PCS is 33 bits. On the PMA interface side, FEC data from and to the PMA interface is 33 bits wide for Firecode FEC and 40 bits for RS-FEC. For designs that include FEC, the gearbox enables automatically. The gearbox mode for Firecode FEC is 32:33 and 32:40 for RS-FEC.

Table 15.  FEC Direct IP Configuration Mode Support
Clocking Mode FEC Mode Double Width/ Single Width 16 PMA Interface Width PMA Interface FIFO (TX/RX) Core Interface FIFO (TX/RX)

System PLL Clocking

Firecode FEC (2112, 2080) CL74 DW 32 Elastic/Elastic Phase Compensation/Phase Compensation
RS-FEC (528, 514) CL108 DW 32 Elastic/Elastic Phase Compensation/Phase Compensation
ETC RS-FEC (528, 514) DW 32 Elastic/Elastic Phase Compensation/Phase Compensation
16 The Double width (DW) mode is when the Enable TX/RX double width transfer parameter in the GTS PMA/FEC Direct PHY IP GUI is enabled. When it is enabled, you can clock the FPGA core logic with a half rate clock. Single width (SW) mode is when this parameter is not enabled.