GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

2.1. Building Blocks

A GTS transceiver bank consists of four PMA channels, hardened IPs (FEC, PCS, PCIe, and Ethernet MAC), a system PLL, and clock networks (for reference clock and datapath clock).
Figure 2. High-Level Block Diagram of a GTS Transceiver Bank

Refer to the following figure for the GTS transceiver bank layout.

Figure 3. GTS Transceiver Bank Layout for C-Series FPGAs with 4 GTS Transceivers
The following table shows the hard IP configurations supported by the PMA for enabling various interface protocols.
Table 2.  Hard IP Configurations Supported with PMA
Configuration PCIe* Hard IP MAC PCS FEC PMA Example Protocols
Hardened PCIe* IP Yes No No No Yes PCIe*
Hardened Ethernet IP No Yes Yes Optional Yes 10G Ethernet
Hardened USB 3.1 IP 2 No No No No Yes USB3.1
PCS Direct No No Yes Optional Yes FlexE
FEC Direct No No No Yes Yes IEEE 802.3 BASE-R Firecode (CL 74), IEEE 802.3 RS(528,514) (CL 108), ETC RS(528,514)
PMA Direct No No No No Yes Basic, HDMI, SDI, DisplayPort 3, JESD204B SATA, GPON 4,
2 The hardened USB 3.1 IP controller resides in the HPS block, and is supported for devices with GTS transceiver and HPS only. Refer to the Agilex™ 3 Hard Processor System Technical Reference Manual for implementation details of USB3.1.
3 The DisplayPort protocol mode is not supported in the GTS PMA/FEC Direct PHY IP. For the complete implementation and solution for the DisplayPort protocol IP, refer to the DisplayPort IP User Guide .
4 SATA and GPON mode are not supported in the current release of the Quartus® Prime Pro Edition software.