GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

2.3.1.1. Transmitter Buffer

A simplified transmitter buffer termination scheme is shown in the following figure.
Figure 9. Simplified TX Buffer Termination
  1. ZTX-DIFF-DC transmitter buffer output differential DC impedance is 90 Ω; 45 Ω single ended.
The transmitter buffer can be programmed to support the taps listed in the following table.
Table 7.  Transmitter PMA Equalizer Parameters
Parameter Cursor Rule Increment and Decrement Size
Minimum Maximum
pre_tap_2 C-2 0 +7 1.0
pre_tap_1 C-1 0 +15 1.0
main_tap C0

C0 = main_tap + 1 - pre_tap_1 -pre_tap_2 - post_tap_1

0 +55 1.0
post_tap_1 C+1 0 +19 1.0
Note: To determine the legal combination of TX equalizer parameter settings, refer to the GTS Transceiver TX Equalization Tool