GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface

The following example shows the RTL connections for a single GTS PMA channel with clock and reset connections and no FPGA core logic driving the additional reconfiguration ports.
Figure 58. Example RTL Connections for a One GTS PMA Lane Design
.i_reconfig_clk          ( i_reconfig_clk    ),  // 100 MHz
.i_reconfig_reset	    ( i_reconfig_reset  ),
.i_reconfig_write	    ( 1'b0	          ),
.i_reconfig_read	     ( 1'b0	          ),
.i_reconfig_address	  ( 17'b0             ),
.i_reconfig_byteenable   ( 4'b0          	),
.i_reconfig_writedata	( 32'b0             ),
.o_reconfig_readdata     ( 	              ),
.o_reconfig_waitrequest  (                   ),
.o_reconfig_readdatavalid(                   )