GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

5.6.1. Example Use Case 1

In this example use case, the device is fully populated and has the following IPs instantiated:
  • GTS Reset Sequencer IP
  • One GTS PMA/FEC Direct PHY IP
  • One GTS Ethernet IP
  • One Triple-Speed Ethernet IP
  • One HPS USB3.1
Table 82.  GTS Reset Sequencer IP Parameter Settings for Use Case 1
Parameter Value Selection
Enable PCIE and/or HPS USB3.1 only design Off
Number of Reset Sequencer Lane(s) 3
Number of Bank(s) 1
The following figure shows the connections between the GTS Reset Sequencer IP and the other instantiated IPs.
Figure 71. Example Use Case 1