GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
ID
848344
Date
8/04/2025
Public
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY IP
3.3. Configuring the GTS PMA/FEC Direct PHY IP
3.4. Dynamically Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. TX Datapath Options
3.3.4. RX Datapath Options
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.6. FEC Options
3.3.7. PCS Options
3.3.8. Avalon® Memory-Mapped Interface Options
3.3.9. Register Map IP-XACT Support
3.3.10. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.7.1. Clock Ports
3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2
3.7.4. PMA Fractional Mode
3.7.5. Input Reference Clock Buffer Protection
3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode)
3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode)
3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA
3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
6.1. Instantiating the GTS PMA/FEC Direct PHY IP
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design
6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design
6.6. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design
6.8. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description
6.9. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench
6.10. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit
8.3.2. Programming the Design into an Altera FPGA
8.3.3. Loading the Design to the Transceiver Toolkit
8.3.4. Creating Transceiver Links
8.3.5. Running BER Tests
8.3.6. Running Eye Viewer Tests
8.3.7. Running Link Optimization Tests
3.3.5.1. PMA Configuration Rules for SDI Mode
You can implement the SDI protocol mode with the GTS PMA/FEC Direct PHY IP by following the steps shown below:
- In the Common Datapath Options select SDI for the PMA configuration rules setting.
- Configure the data rate to match the specific SDI standard you are using.
- Ensure that the reference clock is set to correct frequency to support the SDI data rate.
- Configure the clock dividers to match the SDI data rate.
The following configurations are supported in SDI mode.
Configuration | Data Rate (Mbps) | Refclk Frequencies (MHz) | PMA Data Width |
---|---|---|---|
HD-SDI | 1,485 | 74.25, 148.5 | 20-bit |
1,4835 | 74.175, 148.35 | 20-bit | |
3G-SDI | 2,970 | 148.5, 297 | 20-bit |
2,967 | 148.35, 296.7 | 20-bit | |
6G-SDI | 5,940 | 297, 594 | 20-bit |
12G-SDI | 11,880 | 297, 594 | 20-bit |
If you are implementing the SDI mode, the following are important implementation details:
- Non-bonded mode for SDI: The mode does not use bonded lanes because it transmits video, audio, and data over a single channel, making multi-lane bonding unnecessary.
- RX AC cap bypass: The RX AC coupling on-chip capacitor is bypassed to ensure the receiver can handle the SDI signal's DC components, improving signal quality and reducing distortion. Refer to Receiver Buffer and Equalizer for more information.
- TX PLL fractional mode: If you are implementing parallel loopback without a VCXO, the TX PLL operates in fractional mode with a reference clock frequency of 141 MHz to generate precise clock frequencies needed for accurate data transmission. Refer to TX Datapath Options Parameters for more information on the fractional mode.
You can implement the SDI mode configuration using the GTS PMA/FEC Direct PHY IP and combine it with the GTS SDI II IP, which provides the upper layer protocol implementation, for a complete solution of the SDI protocol. Refer to the GTS SDI II IP Design Example User Guide for more details.
This SDI selection also enables you to implement the dual simplex mode for the GTS PMA/FEC Direct PHY IP. Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for details on how to implement the dual simplex mode.