GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

5.6.2. Example Use Case 2

In this example use case, the device is not fully populated and has the following IPs instantiated:
  • GTS Reset Sequencer IP
  • One GTS AXI Streaming IP for PCI Express*
  • One HPS USB3.1
Table 83.  GTS Reset Sequencer IP Parameter Settings for Use Case 2
Parameter Value Selection
Enable PCIE and/or HPS USB3.1 only design On
Number of Reset Sequencer Lane(s)
Number of Bank(s) 1
The use case also shows you how to use the Enable PCIE and/or HPS USB3.1 only design parameter in a design. In this use case, the i_src_rs_req and o_src_rs_grant ports are not needed but o_pma_cu_clk is still needed and cannot be left unconnected.
Figure 72. Example Use Case 2