GTS AXI Multichannel DMA IP for PCI Express User Guide

ID 847470
Date 5/06/2025
Public

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Document Table of Contents

A.1.1. Multichannel DMA

The GTS AXI Multichannel DMA IP for PCI Express consists primarily of Host-to-Device Data Mover (H2DDM) and Device-to-Host Data Mover (D2HDM) blocks. It also offers a DMA-bypass capability to the Host for doing PIO Reads/Writes to the device memory.

The MCDMA engine operates on a software DMA queue to transfer data between the local FPGA and Host. The elements of each queue are software descriptors that are written by the driver/software. Hardware reads the queue descriptors and executes them. Hardware can support up to 256 DMA channels. For each channel, separate queues are used for read/write DMA operations.