GTS AXI Multichannel DMA IP for PCI Express User Guide

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ID 847470
Date 5/06/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the GTS AXI Multichannel DMA IP for PCI Express 4. Integrating the IP With Your Application 5. Simulating the IP 6. Validating the IP A. Appendix A: Functional Description B. Appendix B: Registers C. Document Revision History for the GTS AXI Multichannel DMA IP for PCI Express*
1. Overview x
1.1. About the GTS AXI Multichannel DMA IP for PCI Express* 1.2. About the Document 1.3. Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Guidelines 1.7. Design Flow Requirements
1.1. About the GTS AXI Multichannel DMA IP for PCI Express* x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. Resource Utilization 1.1.8. IP and Design Example Support
1.1.2. IP Features x
1.1.2.1. Root Port Mode Features 1.1.2.2. Endpoint Mode Features
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training
1.4. Key Concepts x
1.4.1. PCI Express and DMA 1.4.2. Altera FPGA IPs for PCI Express and DMA Controller 1.4.3. Example Use Case
1.6. Design Guidelines x
1.6.1. Supporting IPs 1.6.2. Aligning IP Settings with the GTS AXI Streaming IP for PCI Express
1.7. Design Flow Requirements x
1.7.1. Software Requirements 1.7.2. Hardware Requirements 1.7.3. Supported EDA Tools
2. Quick Start Guide x
2.1. Step-by-step IP Bring-up 2.2. Reset Sequence
2.1. Step-by-step IP Bring-up x
2.1.1. Downloading and Installing Quartus® Prime Software 2.1.2. Configuring and Generating the GTS AXI Multichannel DMA IP for PCI Express 2.1.3. Configuring and Generating the GTS AXI Streaming Intel FPGA IP for PCI Express 2.1.4. Configuring and Generating the GTS System PLL Clocks Intel FPGA IP 2.1.5. Configuring and Generating the GTS Reset Sequencer Intel FPGA IP 2.1.6. Configuring and Generating the Reset Release IP 2.1.7. Instantiating and Connecting the IP Interfaces 2.1.8. Simulate, Compile and Validate the Design on Hardware
2.2. Reset Sequence x
2.2.1. Cold Reset Sequence Triggered by PERST# Signal 2.2.2. Warm Reset Sequence Triggered by Hot Reset 2.2.3. Cold Reset Triggered by User 2.2.4. Warm Reset Triggered by User
3. Configuring and Generating the GTS AXI Multichannel DMA IP for PCI Express x
3.1. Creating the Quartus® Prime Project 3.2. Configuring the GTS AXI Multichannel DMA IP for PCI Express 3.3. Generating HDL for Simulation and Synthesis 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the GTS AXI Multichannel DMA IP for PCI Express x
3.2.1. IP Settings 3.2.2. PCIe Settings
3.2.2. PCIe Settings x
3.2.2.1. MCDMA Settings 3.2.2.2. PCI Express / PCI Capabilities 3.2.2.3. Base Address Registers
3.2.2.1. MCDMA Settings x
3.2.2.1.1. Multichannel DMA Mode 3.2.2.1.2. Bursting Master Mode 3.2.2.1.3. Bursting Slave Mode 3.2.2.1.4. BAM + BAS Mode 3.2.2.1.5. BAM + MCDMA Mode 3.2.2.1.6. BAM + BAS + MCDMA Mode
3.2.2.2. PCI Express / PCI Capabilities x
3.2.2.2.1. PCIe Device 3.2.2.2.2. PCIe MSI-X
3.2.2.2.2. PCIe MSI-X x
3.2.2.2.2.1. PCIe PF MSI-X 3.2.2.2.2.2. PCIe VF MSI-X
3.3. Generating HDL for Simulation and Synthesis x
3.3.1. IP Core Generation Output
4. Integrating the IP With Your Application x
4.1. Overview 4.2. Implementing Required Clocking 4.3. Implementing Required Resets 4.4. Connecting the GTS AXI Streaming IP-Facing Interfaces 4.5. Connect User Logic-Facing Interfaces
4.4. Connecting the GTS AXI Streaming IP-Facing Interfaces x
4.4.1. PCIe AXI-Stream TX Interface (ss_tx_st) 4.4.2. PCIe AXI-Stream RX Interface (ss_rx_st) 4.4.3. Control and Status Register Interface (ss_csr_lite) 4.4.4. Transmit Flow Control Credit Interface (ss_txcrdt) 4.4.5. Configuration Intercept Interface (CII) 4.4.6. Completion Timeout Interface (ss_cplto) 4.4.7. Function Level Reset (FLR) Interface 4.4.8. Control Shadow Interface (ss_ctrlshadow) 4.4.9. Error Interface
4.4.5. Configuration Intercept Interface (CII) x
4.4.5.1. Configuration Intercept Request Interface (ss_cii_req) 4.4.5.2. Configuration Intercept Response Interface (ss_cii_resp)
4.4.7. Function Level Reset (FLR) Interface x
4.4.7.1. FLR Received Interface (ss_flrrcvd) 4.4.7.2. FLR Completion Interface (ss_flrcmpl)
4.5. Connect User Logic-Facing Interfaces x
4.5.1. H2D AXI-Stream Manager (h2d_st_initatr) 4.5.2. D2H AXI-Stream Subordinate (d2h_st_respndr) 4.5.3. H2D/D2H AXI-MM Manager (dma_mm_initatr) 4.5.4. BAM AXI-MM Manager (bam_mm_initatr) 4.5.5. BAS AXI-MM Subordinate (bas_mm_respndr) 4.5.6. PIO AXI-Lite Manager (pio_lite_initiatr) 4.5.7. HIP Reconfiguration AXI-Lite Subordinate (user_csr_lite) 4.5.8. User Event MSI-X (user_msix) 4.5.9. User Event MSI (user_msi) 4.5.10. User Function Level Reset (user_flr) 4.5.11. User Configuration Intercept Interface 4.5.12. Configuration Slave (cs_lite_respndr)
4.5.11. User Configuration Intercept Interface x
4.5.11.1. User Configuration Intercept Request Interface (user_cii_req) 4.5.11.2. User Configuration Intercept Response Interface (user_cii_resp)
5. Simulating the IP x
5.1. Design Example Overview 5.2. Design Example Components 5.3. Simulating the Design Example
5.1. Design Example Overview x
5.1.1. AXI-S Device-side Packet Loopback Design Example
6. Validating the IP x
6.1. Hardware and Software Requirements 6.2. Running the Design Example Application on a Hardware Setup
6.2. Running the Design Example Application on a Hardware Setup x
6.2.1. Program the FPGA 6.2.2. Configuration Changes from BIOS 6.2.3. Host Operating System Check (if Working with Ubuntu 22.04) 6.2.4. Installing the Required Kernel Version (if Working with Ubuntu 24.04) 6.2.5. Set the Boot Parameters 6.2.6. Custom Driver 6.2.7. DPDK Poll Mode Driver
6.2.6. Custom Driver x
6.2.6.1. Prerequisites 6.2.6.2. PIO Test 6.2.6.3. Custom PIO Read Write Test 6.2.6.4. DMA Test
6.2.6.1. Prerequisites x
6.2.6.1.1. Steps for UIO Driver Installation 6.2.6.1.2. Enable Virtual Function 6.2.6.1.3. Build and Install User Space Library 6.2.6.1.4. Build the Reference Application
6.2.6.4. DMA Test x
6.2.6.4.1. AXI-S Device-side Packet Loopback (Device-side Packet Loopback)
6.2.7. DPDK Poll Mode Driver x
6.2.7.1. Prerequisites 6.2.7.2. PIO Test 6.2.7.3. DMA Test
6.2.7.1. Prerequisites x
6.2.7.1.1. Install PMD Driver 6.2.7.1.2. Bind the Device 6.2.7.1.3. Enable Virtual Function
6.2.7.3. DMA Test x
6.2.7.3.1. Device-side Packet Loopback
A. Appendix A: Functional Description x
A.1. High-level Functional Overview
A.1. High-level Functional Overview x
A.1.1. Multichannel DMA A.1.2. Bursting Master (BAM) A.1.3. Bursting Slave (BAS) A.1.4. MSI Interrupt A.1.5. Configuration Slave (CS) A.1.6. Root Port Address Translation Table Enablement A.1.7. Control and Status Register Interface A.1.8. Configuration Intercept Interface
A.1.1. Multichannel DMA x
A.1.1.1. H2D Data Mover A.1.1.2. D2H Data Mover A.1.1.3. Descriptors A.1.1.4. AXI4-Lite PIO Manager A.1.1.5. AXI-MM Write (H2D) and Read (D2H) Manager A.1.1.6. AXI-Stream Manager (H2D) and Subordinate (D2H) A.1.1.7. User MSI-X A.1.1.8. User Function Level Reset (FLR) A.1.1.9. Control and Status Registers
A.1.1.2. D2H Data Mover x
A.1.1.2.1. D2H Descriptor Fetch
A.1.1.3. Descriptors x
A.1.1.3.1. Support for Unaligned (or Byte-Aligned) Data Transfer A.1.1.3.2. Metadata Support A.1.1.3.3. MSI-X/Writeback
A.1.4. MSI Interrupt x
A.1.4.1. Endpoint MSI Support Through BAS A.1.4.2. MSI Interrupt Controller
A.1.5. Configuration Slave (CS) x
A.1.5.1. 14-bit AXI-MM Address Format A.1.5.2. Configuration Access Mechanism
B. Appendix B: Registers x
B.1. Queue Control B.2. MSI-X Memory Space B.3. Control Register (GCSR)
1. Overview
2. Quick Start Guide
3. Configuring and Generating the GTS AXI Multichannel DMA IP for PCI Express
4. Integrating the IP With Your Application
5. Simulating the IP
6. Validating the IP
A. Appendix A: Functional Description
B. Appendix B: Registers
C. Document Revision History for the GTS AXI Multichannel DMA IP for PCI Express*

3.4. Generating the Design Example

In the Quartus® Prime Pro Edition software, you can generate a design example for the GTS AXI Multichannel DMA IP for PCI Express.

Figure 23. Design Example Generation
Following is the procedure to generate a design example:
  1. In the Quartus® Prime Pro Edition software, create a new project by clicking File → New Project Wizard. Click Next.
  2. Select Empty Project type and specify the Directory, Name, and Top-Level Entity. Click Next.
  3. Specify the Family, Device & Board Settings as follows:
    1. Select Family: Agilex™ 5 (E-Series/D-Series).
    2. Select Target device: A5ED065BB32AE4SR0.
      Note: The device used for the Quartus® Prime-generated design example matches the device used in the target FPGA development kit board and may not be the same as the target device selected here.
    3. Click Finish.
  4. Select from Tools → IP Catalog to open the IP Catalog.
  5. Select GTS AXI Multichannel DMA IP for PCI Express (Library → Interface Protocols → PCI Express → GTS AXI Multichannel DMA IP for PCI Express) and then click Add.
  6. In the New IP Variant dialogue box, specify a top-level name for your new custom IP variation and the directory for it. The IP Parameter Editor saves the IP variation settings in a file named <your_ip>.ip.
  7. Click Create. The IP Parameter Editor appears as shown in the figure below.
  8. Go to the Example Designs tab, and make the following selections:
    1. For Example Design Files, the Simulation and Synthesis options are turned on by default. Leave the settings in default, unless you do not need the simulation or synthesis files, and to reduce the design example generation time.
      Note: The design example does not support simulation in this release. Turn off the Simulation option to reduce the design example generation time.
    2. For Generated HDL Format, only Verilog is supported in the current release.
    3. For Target Development Kit, select either the Agilex 5 FPGA E-Series 065B Modular Development Kit (ES1) or NONE to target the device selected for your current Quartus® Prime software project.
      Note: If you select the development kit, the settings including the target device, pin assignments are included in the .qsf file of the generated design example, and you are not required to add them manually. These settings are board-specific for the development kit.
      Note: Agilex 5 FPGA E-Series 065B Modular Development Kit option is not supported for the Gen4 1x4 mode design example in the current release.
    4. For Currently Selected Example Design, only the AXI-S Device-side Packet Loopback variant is supported in this release.
    Table 30.  Design Example Parameters
    Parameter Value Default Value Description
    Simulation On / Off On Design example simulation is not supported in the current release.
    Synthesis   On When the Synthesis box is checked, all necessary file sets for synthesis are generated. When unchecked, only the Platform Designer system is generated.
    Generated file format Verilog Verilog HDL format.
    Current development kit

    Agilex 5 FPGA E-Series 065B Modular Development Kit (ES1)

    None

    		Agilex 5 FPGA E-Series 065B Modular Development Kit (ES1)

    Selects a target FPGA development kit board.

    Note: If an FPGA development board is selected, the target device used for generation is the one that matches the device on the development kit board.
    Note: Agilex 5 FPGA E-Series 065B Modular Development Kit option is not supported for the Gen4 1x4 mode design example in the current release.
    Enable PIPE Mode Simulation for Example Design On / Off On When selected, PIPE mode simulation is enabled.
    Currently selected example design AXI-S Device-side Packet Loopback AXI-S Device-side Packet Loopback

    Selects example design variant. Only the AXI-S Device-side Packet Loopback example design is supported in the current release.

    Note:
    • Design examples for BAM, BAS, BAM+BAS, BAM+MCDMA, and BAM+BAS+MCDMA modes are not supported.
    • Design example for Root Port mode is not supported.
    Note: Design example generation includes the GTS AXI Streaming Intel FPGA IP for PCI Express (intel_pcie_gts). Hence, the Example Designs tab includes the GTS AXI Streaming IP Parameter Editor. Some of the PCIe Interface parameters are automatically configured per the GTS AXI MCDMA IP parameter values and greyed out.
    Table 31.  PCIe Interface Settings Parameters
    Parameter Value Default Value Description
    Hard IP Mode Gen4 x4 Interface 256-bit

    Gen3 x4 Interface 128-bit

    		Gen4 x4 Interface 256-bit Selects the PCIe Hard IP mode.
    Note: The ode value is passed from the GTS AXI MCDMA IP settings.
    Enable TLP-Bypass Mode On / Off Off Enables the TLP Bypass feature for the GTS AXI Streaming IP.
    Note: The TLP Bypass design example is not supported.
    Port Mode Root Port

    Native Endpoint

    		Native Endpoint Selects a PCIe mode for the GTS AXI Streaming IP.
    Note: The mode value is passed from the AXI MCDMA IP Settings.
    Note: The Root Port design example is not supported.
    PLD Clock Frequency

    Gen4 1x4: 350/300/250/200 MHz

    Gen3 1x4: 300/250/200 MHz

    		300 MHz

    Selects the PLD clock frequency.
    Enable SRIS Mode Off Off Enables the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.
    Enable PIPE Mode Simulation On / Off Off When on, this parameter enables the PIPE mode simulation.
    Enable CVP (Intel VSEC) On / Off Off Enables the CVP feature for the GTS AXI Streaming IP.
  9. Click on Generate Example Design to generate the design example variant. When the prompt asks you to specify the directory for your design example, you can accept the default directory, /pcie_gts_mcdma_0_example_design, or choose another directory. Then, click OK to kick off the design example generation.
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