GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 4/01/2024
Public

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4.8.1. Time-of-Day Interface

The shared time-of-day (TOD) allows the IP core to reference all timestamps to the local time-of-day. The 96-bit timestamps are in IEEE 1588 v2 format.

Table 36.  Time-of-Day (TOD) Interface SignalsThe Time-of-Day interface allows the IP core to reference all of its timestamps to the local Time of Day.
Port Name Width Domain Description
i_ptp_tx_tod[95:0] 96 i_clk_tx_tod

Time of Day according to the Local Clock for TX clock domain.

This bus is used to present the current time of day (according to the local clock) to the TX data path of Ethernet Core.

The format of the time is IEEE 1588v2 (96 bits)

[95:48]: Seconds

[47:16]: Nanoseconds

[15:0]: Fractional nanoseconds

i_ptp_tx_tod_valid 1 i_clk_tx_tod

Indicates TX Time of Day is valid

Assert this signal when i_ptp_tx_tod contains valid time.

Deassert this signal for at least one clock cycle to indicate that there is a significant change in i_ptp_tx_tod value, i.e.: due to reset of time-of-day or first time-of-day adjustment after system power up. IP will deassert o_tx_ptp_ready to indicate TX egress timestamp is not valid.

i_ptp_rx_tod[95:0] 96 i_clk_rx_tod

Time of Day according to the Local Clock for RX clock domain.

This bus is used to present the current time of day (according to the local clock) to the RX data path of Ethernet Core.

The format of the time is IEEE 1588v2 (96 bits)

[95:48]: Seconds

[47:16]: Nanoseconds

[15:0]: Fractional nanoseconds

i_ptp_rx_tod_valid 1 i_clk_rx_tod

Indicates RX Time of Day is valid

Assert this signal when i_ptp_rx_tod contains valid time.

Deassert this signal for at least one clock cycle to indicate that there is a significant change in i_ptp_rx_tod value, i.e.: due to reset of time-of-day or first time-of-day adjustment after system power up. IP will deassert o_rx_ptp_ready to indicate RX ingress timestamp is not valid.