GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. GTS Ethernet Intel® FPGA Hard IP Parameters 4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application 5. Functional Description 6. Configuration Registers 7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Agilex™ 5 Ethernet Portfolio and Target Applications 1.2. Agilex™ 5 Ethernet Hard IP Features 1.3. High-Level Functional Overview 1.4. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.2. Agilex™ 5 Ethernet Hard IP Features x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-Trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing GTS Ethernet Intel® FPGA Hard IP Cores 2.2. Generate HDL for Synthesis and Simulation 2.3. Generated File Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application x
4.1. Clocks 4.2. Resets 4.3. MAC Client Interface – Avalon® Streaming Interface 4.4. PCS Client Interface – MII PCS Only 4.5. PCS66 Client Interface – FlexE and OTN 4.6. Connect the Status Interface 4.7. Ethernet Hard IP Reconfiguration Interface 4.8. Precision Time Protocol Interface
4.1. Clocks x
4.1.1. MAC Synchronous Clock Connections to Single Instance 4.1.2. MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Clock Connections to MAC Asynchronous Operation 4.1.4. Clock Connections in PTP-Based Synchronous Operation 4.1.5. Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.6. I/O PLL as System PLL
4.2. Resets x
4.2.1. Reset Signals 4.2.2. Reset Sequence 4.2.3. Power Up Reset Sequence 4.2.4. TX Reset Entry Sequence 4.2.5. TX Reset Exit Sequence 4.2.6. RX Reset Entry Sequence 4.2.7. RX Reset Exit Sequence 4.2.8. Auto Recovery Reset Sequence 4.2.9. GTS Reset Sequencer Intel® FPGA IP
4.2.9. GTS Reset Sequencer Intel® FPGA IP x
4.2.9.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. MAC Client Interface – Avalon® Streaming Interface x
4.3.1. TX MAC Avalon Streaming Client Interface 4.3.2. RX MAC Avalon Streaming Client Interface 4.3.3. MAC Flow Control Interface
4.3.1. TX MAC Avalon Streaming Client Interface x
4.3.1.1. TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.1.2. TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.3.1.3. Control Source Address, PAD, and CRC Insertion 4.3.1.4. Assert the i_tx_error to Invalidate a Packet
4.3.2. RX MAC Avalon Streaming Client Interface x
4.3.2.1. RX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.2.2. Enable Preamble Passthrough and RX CRC Forwarding 4.3.2.3. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.3.3. MAC Flow Control Interface x
4.3.3.1. TX PAUSE and TX PFC Ports 4.3.3.2. Receiving PAUSE and PFC Frames
4.4. PCS Client Interface – MII PCS Only x
4.4.1. PCS Mode TX Interface 4.4.2. PCS Mode RX Interface
4.5. PCS66 Client Interface – FlexE and OTN x
4.5.1. FlexE and OTN Mode TX Interface 4.5.2. FlexE and OTN Mode RX Interface
4.6. Connect the Status Interface x
4.6.1. Status Interface
4.8. Precision Time Protocol Interface x
4.8.1. Time-of-Day Interface 4.8.2. TX 2-Step Timestamp Interface 4.8.3. TX 1-Step Timestamp Interface 4.8.4. RX Timestamp Interface 4.8.5. PTP Status Interface
4.8.3. TX 1-Step Timestamp Interface x
4.8.3.1. PTP Field Offset for 1-Step Operation
5. Functional Description x
5.1. Datapath Description 5.2. GTS Ethernet Intel® FPGA Hard IP MAC 5.3. PCS, OTN, and FlexE Modes 5.4. Precision Time Protocol Interface
5.2. GTS Ethernet Intel® FPGA Hard IP MAC x
5.2.1. MAC TX Datapath 5.2.2. MAC RX Datapath 5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 5.2.4. Link Fault Signaling 5.2.5. Order of Ethernet Transmission:
5.2.1. MAC TX Datapath x
5.2.1.1. TX Preamble, Start, and SFD Insertion 5.2.1.2. Source Address Insertion 5.2.1.3. Length/Type Field Processing 5.2.1.4. Frame Padding 5.2.1.5. Frame Check Sequence (CRC-32) Insertion 5.2.1.6. Inter-Packet Gap Generation and Insertion
5.2.2. MAC RX Datapath x
5.2.2.1. RX Preamble Processing 5.2.2.2. RX Strict SFD Checking 5.2.2.3. RX FCS Checking 5.2.2.4. RX Malformed Packet Handling 5.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 5.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 5.2.2.7. Inter-Packet Gap
5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
5.2.3.1. Conditions Triggering XOFF Frame Transmission 5.2.3.2. Conditions Triggering XON Frame Transmission 5.2.3.3. Pause Control and Generation Interface 5.2.3.4. Pause Control Frame Filtering
5.3. PCS, OTN, and FlexE Modes x
5.3.1. PCS Mode 5.3.2. OTN Mode 5.3.3. FlexE Mode
5.4. Precision Time Protocol Interface x
5.4.1. Features 5.4.2. PTP User Flow 5.4.3. UI Adjustment 5.4.4. Reference Time Interval 5.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
5.4.2. PTP User Flow x
5.4.2.1. PTP TX User Flow 5.4.2.2. PTP RX User Flow
5.4.3. UI Adjustment x
5.4.3.1. TX UI Adjustment 5.4.3.2. RX UI Adjustment
6. Configuration Registers x
6.1. Ethernet Avalon® Memory-Mapped Interface Address Space 6.2. GTS Ethernet Intel® FPGA Hard IP Core CSRs 6.3. Transceiver Avalon® Memory-Mapped Interface Address Space
1. Overview
2. Getting Started
3. GTS Ethernet Intel® FPGA Hard IP Parameters
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application
5. Functional Description
6. Configuration Registers
7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

5.4.2.1. PTP TX User Flow

In this section, the acronyms PL and VL stand for Physical Lane and Virtual Lane respectively.

The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.

Important: If IP undergoes TX reset at any point in this flow, you must restart the entire PTP TX client flow.
  1. After power up or a TX reset, wait until TX raw offset data are ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_offset_data_valid = 1'b1
    • Polling via Avalon® memory-mapped interface register until it is asserted:
      csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
  2. Read TX raw offset data from IP:
    tx_const_delay      = csr_read(ptp_tx_lane_calc_data_constdelay[30:0])
tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31])
tx_apulse_offset = csr_read(ptp_tx_lane_calc_data_offset[30:0])
 tx_apulse_offset_sign = csr_read(ptp_tx_lane_calc_data_offset[31])
 tx_apulse_wdelay = csr_read(ptp_tx_lane_calc_data_wiredelay[19:0]) }
  3. Calculate TX offsets:
    1. Calculate TX TAM adjust:
      tx_tam_adjust = 
  (tx_const_delay_sign ? –tx_const_delay : tx_const_delay)
+ (tx_apulse_offset_sign? 
      –tx_apulse_offset : tx_apulse_offset)
– (tx_apulse_wdelay)
      Note: Convert TAM adjust to a 32-bit 2's complement number: 
      tx_tam_adjust_2c = tx_tam_adjust
    2. Calculate TX extra latency:
      Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay. 
      tx_pma_delay_ns = tx_pma_delay_ui * UI4
      TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together: 
      tx_extra_latency[31] = 1'b0
tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
  4. Write the calculated TX offsets to IP:
    1. Write TX extra latency:
      csr_write(tx_ptp_extra_latency, tx_extra_latency)
    2. Write TX TAM adjust:
      csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
  5. UI value measurement. Follow the steps mentioned in the TX UI Adjustment section.

    For simulation or hardware run with 0 ppm setup, you can skip the measurement and program 0 ppm UI value defined in UI Adjustment.

  6. Notify soft PTP that user flow configuration is complete.
    csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
  7. Wait until TX PTP is ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_ready = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.tx_ptp_ready) = 1’b1
  8. TX PTP is up and running.
    1. Adjust TX UI value.

      Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in TX UI Adjustment .

      Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 ppm value.
4 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's max value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.
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