GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. GTS Ethernet Intel® FPGA Hard IP Parameters 4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application 5. Functional Description 6. Configuration Registers 7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Agilex™ 5 Ethernet Portfolio and Target Applications 1.2. Agilex™ 5 Ethernet Hard IP Features 1.3. High-Level Functional Overview 1.4. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.2. Agilex™ 5 Ethernet Hard IP Features x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-Trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing GTS Ethernet Intel® FPGA Hard IP Cores 2.2. Generate HDL for Synthesis and Simulation 2.3. Generated File Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application x
4.1. Clocks 4.2. Resets 4.3. MAC Client Interface – Avalon® Streaming Interface 4.4. PCS Client Interface – MII PCS Only 4.5. PCS66 Client Interface – FlexE and OTN 4.6. Connect the Status Interface 4.7. Ethernet Hard IP Reconfiguration Interface 4.8. Precision Time Protocol Interface
4.1. Clocks x
4.1.1. MAC Synchronous Clock Connections to Single Instance 4.1.2. MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Clock Connections to MAC Asynchronous Operation 4.1.4. Clock Connections in PTP-Based Synchronous Operation 4.1.5. Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.6. I/O PLL as System PLL
4.2. Resets x
4.2.1. Reset Signals 4.2.2. Reset Sequence 4.2.3. Power Up Reset Sequence 4.2.4. TX Reset Entry Sequence 4.2.5. TX Reset Exit Sequence 4.2.6. RX Reset Entry Sequence 4.2.7. RX Reset Exit Sequence 4.2.8. Auto Recovery Reset Sequence 4.2.9. GTS Reset Sequencer Intel® FPGA IP
4.2.9. GTS Reset Sequencer Intel® FPGA IP x
4.2.9.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. MAC Client Interface – Avalon® Streaming Interface x
4.3.1. TX MAC Avalon Streaming Client Interface 4.3.2. RX MAC Avalon Streaming Client Interface 4.3.3. MAC Flow Control Interface
4.3.1. TX MAC Avalon Streaming Client Interface x
4.3.1.1. TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.1.2. TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.3.1.3. Control Source Address, PAD, and CRC Insertion 4.3.1.4. Assert the i_tx_error to Invalidate a Packet
4.3.2. RX MAC Avalon Streaming Client Interface x
4.3.2.1. RX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.2.2. Enable Preamble Passthrough and RX CRC Forwarding 4.3.2.3. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.3.3. MAC Flow Control Interface x
4.3.3.1. TX PAUSE and TX PFC Ports 4.3.3.2. Receiving PAUSE and PFC Frames
4.4. PCS Client Interface – MII PCS Only x
4.4.1. PCS Mode TX Interface 4.4.2. PCS Mode RX Interface
4.5. PCS66 Client Interface – FlexE and OTN x
4.5.1. FlexE and OTN Mode TX Interface 4.5.2. FlexE and OTN Mode RX Interface
4.6. Connect the Status Interface x
4.6.1. Status Interface
4.8. Precision Time Protocol Interface x
4.8.1. Time-of-Day Interface 4.8.2. TX 2-Step Timestamp Interface 4.8.3. TX 1-Step Timestamp Interface 4.8.4. RX Timestamp Interface 4.8.5. PTP Status Interface
4.8.3. TX 1-Step Timestamp Interface x
4.8.3.1. PTP Field Offset for 1-Step Operation
5. Functional Description x
5.1. Datapath Description 5.2. GTS Ethernet Intel® FPGA Hard IP MAC 5.3. PCS, OTN, and FlexE Modes 5.4. Precision Time Protocol Interface
5.2. GTS Ethernet Intel® FPGA Hard IP MAC x
5.2.1. MAC TX Datapath 5.2.2. MAC RX Datapath 5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 5.2.4. Link Fault Signaling 5.2.5. Order of Ethernet Transmission:
5.2.1. MAC TX Datapath x
5.2.1.1. TX Preamble, Start, and SFD Insertion 5.2.1.2. Source Address Insertion 5.2.1.3. Length/Type Field Processing 5.2.1.4. Frame Padding 5.2.1.5. Frame Check Sequence (CRC-32) Insertion 5.2.1.6. Inter-Packet Gap Generation and Insertion
5.2.2. MAC RX Datapath x
5.2.2.1. RX Preamble Processing 5.2.2.2. RX Strict SFD Checking 5.2.2.3. RX FCS Checking 5.2.2.4. RX Malformed Packet Handling 5.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 5.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 5.2.2.7. Inter-Packet Gap
5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
5.2.3.1. Conditions Triggering XOFF Frame Transmission 5.2.3.2. Conditions Triggering XON Frame Transmission 5.2.3.3. Pause Control and Generation Interface 5.2.3.4. Pause Control Frame Filtering
5.3. PCS, OTN, and FlexE Modes x
5.3.1. PCS Mode 5.3.2. OTN Mode 5.3.3. FlexE Mode
5.4. Precision Time Protocol Interface x
5.4.1. Features 5.4.2. PTP User Flow 5.4.3. UI Adjustment 5.4.4. Reference Time Interval 5.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
5.4.2. PTP User Flow x
5.4.2.1. PTP TX User Flow 5.4.2.2. PTP RX User Flow
5.4.3. UI Adjustment x
5.4.3.1. TX UI Adjustment 5.4.3.2. RX UI Adjustment
6. Configuration Registers x
6.1. Ethernet Avalon® Memory-Mapped Interface Address Space 6.2. GTS Ethernet Intel® FPGA Hard IP Core CSRs 6.3. Transceiver Avalon® Memory-Mapped Interface Address Space
1. Overview
2. Getting Started
3. GTS Ethernet Intel® FPGA Hard IP Parameters
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application
5. Functional Description
6. Configuration Registers
7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

4.3.3. MAC Flow Control Interface

The GTS Ethernet Intel® FPGA Hard IP MAC flow control interface in MAC Avalon® ST configuration indicates and receives flow control event notifications.

Table 26.  MAC Flow Control InterfaceAll interface signals are clocked by the i_clk_tx clock. For 10GE/25GE channels, all interface signals are asynchronous.
Signal Name Width Description
i_tx_pause 1 bit

When asserted, directs the IP core to send a PAUSE XOFF frame on the Ethernet link.

Note: For 10GE/25GE channels, you should hold the i_tx_pause signal more than 205ns to get the request captured by the MAC.
i_tx_pfc[7:0] 8 bits

When a bit is asserted, directs the IP core to send a PFC XOFF frame on the Ethernet link for the corresponding priority queue.

Note: For 10GE/25GE channels, you should hold the i_tx_pfc signal more than 205 ns to get the request captured by the MAC.

The rising edge triggers the request. You must maintain this signal at the value of 1 until you want the IP core to end the pause period. The IP core sends a PFC XOFF frame after it completes processing of the current in-flight TX packet, and periodically thereafter, until you deassert thei_tx_pfc bit. When you deassert the bit, the IP core sends a PFC XON frame on the Ethernet link for the corresponding priority queue. This signal is functional only if priority flow control is enabled.

o_rx_pause 1 bit When asserted, indicates the IP core received a PAUSE XOFF frame on the Ethernet link.
o_rx_pfc[7:0] 8 bits When a bit is asserted, indicates the IP core received a PFC XOFF frame on the Ethernet link for the corresponding priority queue.

Section Content
TX PAUSE and TX PFC Ports
Receiving PAUSE and PFC Frames

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