GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 4/01/2024
Public

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Document Table of Contents

5.4.2.2. PTP RX User Flow

In this section, the acronyms PL and VL stand for Physical Lane and Virtual Lane respectively.

The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.
Note: The RX PTP Ready signal is deasserted when TX Reset is asserted. The RX PTP Ready signal asserts once TX Reset is released without the need to perform the initialization flow, provided the RX link is not lost or RX reset is not asserted during the TX Reset interval.
  1. After power on or RX reset or reestablish a lost RX link, wait until RX PCS is fully aligned.
    You can monitor the status via one of the following:
    • Output port:
      o_rx_pcs_fully_alligned = 1'b1
    • Polling via Avalon® memory-mapped interface register until it is asserted:
      • For 10GE and 25G FEC variants:
        csr_read(phy_rxpcs_status.rx_aligned) = 1’b1
  2. For FEC variants, configure RX FEC codeword position into the transceiver.
    Attention: You must skip this step for non-FEC variants.
    1. Read RX FEC codeword position and FEC channel mapping for each PMA channel.
      rx_fec_cw_pos = csr_read(rsfec_cw_pos_rx[fl][14:0])
    2. Calculate pulse adjustments
      rx_xcvr_if_pulse_adj = rx_fec_cw_pos
    3. Write the pulse adjustments into the IP:
      csr_write(ux_q_dl_ctrl_a_l<apl>.cfg_rx_lat_bit_for_async[17:0], 
                   rx_xcvr_if_pulse_adj[pl*pl_fl_map])
      
      Note: Each bank has one actual physical channel. You must program the registers of all active bank channels.
    4. Notify soft PTP that pulse adjustments have been configured.
      csr_write(ptp_rx_user_cfg_status.rx_fec_cw_pos_cfg_done, 1'b1)
  3. Wait until RX raw offset data are ready.
    You can monitor the status via one of the following:
    • Output port:
      o_rx_ptp_offset_data_valid = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.rx_ptp_offset_data_valid) = 1’b1
  4. Read RX raw offset data from IP:
    • All variants:
      rx_const_delay = csr_read(ptp_rx_lane_calc_data_constdelay[30:0])
      rx_const_delay_sign = csr_read(ptp_rx_lane_calc_data_constdelay[31])
      
       rx_apulse_offset = csr_read(ptp_rx_lane_calc_data_offset[30:0])
       rx_apulse_offset_sign = csr_read(ptp_rx_lane_calc_data_offset[31])
       rx_apulse_wdelay] = csr_read(ptp_rx_lane_calc_data_wiredelay[19:0])
       
    • 10GE/25GE no FEC variants:
      rx_bitslip_cnt       = csr_read(bitslip_cnt.bitslip_cnt[6:0])
      rx_dlpulse_alignment = csr_read(bitslip_cnt.dlpulse_alignment)
      
  5. Determine synchronous pulse (Alignment Marker (AM)) offsets with reference to asynchronous pulse.
    • FEC variants:
      	 rx_spulse_offset = rx_xcvr_if_pulse_adj[4:0] * UI 
      	 rx_spulse_offset_sign = 1'b0;
  6. Calculate RX offsets:
    1. Calculate RX TAM adjust:
      FEC variants:
      rx_tam_adjust = 
         (rx_const_delay_sign ? –rx_const_delay : rx_const_delay) 
       + (rx_apulse_offset_sign ? 
           –rx_apulse_offset : rx_apulse_offset
       – (rx_apulse_wdelay)
       + (rx_spulse_offset_sign ? 
           -rx_spulse_offset[rx_ref_fl] : rx_spulse_offset[rx_ref_fl])
      For all other cases:
      rx_tam_adjust = rx_tam_adjust_sim 

      Convert TAM adjust to a 32-bit 2's complement number:

      rx_tam_adjust_2c = rx_tam_adjust
      where rx_tam_adjust is a 32-bit 2's complement number
    2. Calculate RX extra latency:
      Convert unit of RX PMA delay from UI to nanoseconds:
      rx_pma_delay_ns = rx_pma_delay_ui * UI5
      RX extra latency is a negative adjustment. To indicate the negative adjustment, set the most-significant register bit to 1. Total up all extra latency together:
      rx_extra_latency[30:0] = rx_pma_delay_ns + rx_external_phy_delay
      rx_extra_latency[31] = 1'b1
  7. Write the calculated RX offsets to IP:
    1. Write RX extra latency:
      csr_write(rx_ptp_extra_latency, rx_extra_latency)
    2. Write RX TAM adjust:
      csr_write(ptp_rx_tam_adjust, rx_tam_adjust_2c)
  8. Notify soft PTP that uses flow configuration is completed.
    csr_write(ptp_rx_user_cfg_status.rx_user_cfg_done, 1'b1)
  9. Continue UI value measurement. Follow steps 1 through 7 mentioned in the RX UI Adjustment section.

    For simulation or hardware run with 0 ppm setup, you can skip the measurement and program 0 ppm UI value defined in UI Adjustment.

  10. Wait until RX PTP is ready.
    You can monitor the status via one of the following:
    • Output port:
      o_rx_ptp_ready = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.rx_ptp_ready) = 1’b1
  11. RX PTP is up and running.
    1. Adjust RX UI value.

      Perform the RX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow steps 1 through 8 described in RX UI Adjustment.

      Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 ppm value. For more details, refer to UI Value and PMA Delay.
5 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's max value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.