GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 4/01/2024
Public

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6. Configuration Registers

You can use the Avalon® Memory-Mapped Interface Ethernet reconfiguration interface to access the Ethernet registers within the GTS Ethernet Intel® FPGA Hard IP on each channel. These registers use 32-bit addresses, and you can use a byte enabled signal to address individual bytes. The GTS Ethernet Intel® FPGA Hard IP register addresses are byte-addressable.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have an undefined effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.