F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents Transceiver Native PHY Signal

Table 83.  Transceiver Native PHY Signal
Name I/O Description
cdr_ref_clk_n I Port to connect the RX PLL reference clock with a frequency of 125 MHz when you enable SyncE support.