F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 8/16/2024
Public
Document Table of Contents

2.3. Features

  • Complete Triple-Speed Ethernet IP: 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.
  • 10/100/1000 Mbps Ethernet MAC features:
    • Multiple variations: 10/100/1000 Mbps Ethernet MAC in full duplex, 10/100 Mbps Ethernet MAC in half duplex, 10/100 Mbps or 1000 Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.
    • Support for basic, virtual LAN (VLAN), stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames.
    • Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.
    • Optional statistics counters.
  • MAC interfaces:
    • Client side—8 bit or 32 bit Avalon® streaming interface
    • Network side—MII or GMII on the network side. Optional loopback on these interfaces.
    • Optional management data input/output (MDIO) master interface for PHY device management.
  • 1000BASE-X/SGMII PCS features:
    • Compliance with Clause 36 of the IEEE standard 802.3.
    • Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft clock data recovery (CDR) in Altera FPGA devices that support this interface at 1.25 Gbps data rate.
    • Support for auto-negotiation as defined in Clause 37.
    • Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-T PHYs if the PHYs support SGMII.
  • PCS interfaces:
    • Client side—MII or GMII
    • Network side—ten-bit interface (TBI) for PCS without PMA; 1.25 Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera FPGA devices that support this interface at 1.25 Gbps data rate.
  • Programmable features via 32 bit configuration registers:
    • FIFO buffer thresholds.
    • Pause quanta for flow control.
    • Source and destination MAC addresses.
    • Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.
    • Promiscuous mode—receive frame filtering is disabled in this mode.
    • Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS (with or without MAC), the frame length is up to 10 Kbytes.
    • Optional auto-negotiation for the 1000BASE-X/SGMII PCS.
  • Error correction code protection feature for internal memory blocks.
  • Optional IEEE 1588v2 feature for 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and embedded serial PMA variation operating without internal FIFO buffer in full-duplex mode.