F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents Programmable 10/100/1000 Ethernet Operation

Typically, 10/100/1000 Ethernet PHY devices implement a shared interface that you connect to a 10/100-Mbps MAC via MII/RGMII.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz, or 125 MHz) to the MAC clock, rx_clk. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode selects either MII or GMII. The MAC function asserts the eth_mode signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.

Figure 27. 10/100/1000 PHY Interface via MII/GMII