F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents PHY Management Signals

Table 57.  PHY Management Interface Signals
Name I/O Description
mdio_in I Management data input.
mdio_out O Management data output.
mdio_oen O An active-low signal that enables mdio_in or mdio_out. For more information about the MDIO connection, refer to MDIO Connection.
mdc O Management data clock. Generated from the Avalon® memory-mapped interface clock signal, clk. Specify the division factor using the Host clock divisor parameter such that the frequency of this clock does not exceed 2.5 MHz. For more information about the parameters, refer to Ethernet MAC Options.

A data bit is shifted in/out on each rising edge of this clock. All fields are shifted in and out starting from the most significant bit.