F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents

7.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals

Figure 55. 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS With Embedded PMA Signals
  1. The SERDES control signals are present in variations targeting devices with GX transceivers.
  2. The DATAWIDTH value depends on the FIFO width that you select in the parameter editor. Options available are 8 and 32 bits.