F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 8/16/2024
Public
Document Table of Contents

2.7. IP Verification

For each release, Intel verifies the Triple-Speed Ethernet Intel® FPGA IP through extensive simulation and internal hardware verification in various Intel FPGA device families. The University of New Hampshire InterOperability Lab also successfully verified the IP prior to its release.

Intel used a highly parameterizable transaction-based testbench to test the following aspects of the IP:

  • Register access
  • MDIO access
  • Frame transmission and error handling
  • Frame reception and error handling
  • Ethernet frame MAC address filtering
  • Flow control
  • Retransmission in half-duplex