F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents

5.2.9. 1000BASE-X/SGMII PCS Reset

A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only resets the PCS state machines, comma detection function, and 8B10B encoder and decoder. To trigger a hardware reset on the PCS, assert the respective reset signals: reset_reg_clk, reset_tx_clk, and reset_rx_clk. To trigger a software reset, set the RESET bit in the control register to 1.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset signal after asserting the reset_rx_clk or reset_tx_clk signal. The reset sequence is also initiated when the active-low rx_freqlocked signal goes low.

Figure 37. Reset Distribution in PCS with Embedded PMA

For more information about the rx_freqlocked signal and transceiver reset, refer to the transceiver handbook of the respective device family.

Assert the reset signals to perform a hardware reset on MAC with PCS and embedded PMA variation.

Note: You must assert the reset signal for at least three clock cycles.
Figure 38. Reset Distribution in MAC with PCS and Embedded PMA