F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents

7.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals

Figure 56. 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers 1000BASE-X/SGMII PCS and Embedded PMA Signals
Note: The SERDES control signals are present in variations targeting devices with GX transceivers.
Table 85.  References
Interface Signal Section
Clock and reset signals Clock and Reset Signals
MAC control interface MAC Control Interface Signals
MAC transmit interface MAC Transmit Interface Signals
MAC receive interface MAC Receive Interface Signals
MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Pause and magic packet signals Pause and Magic Packet Signals
PHY management signals PHY Management Signals
1.25 Gbps serial signals 1.25 Gbps Serial Signals
Status LED control signals Status LED Control Signals
SERDES control signals SERDES Control Signals
Transceiver Native PHY signal Transceiver Native PHY Signal