F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents

7.1.12. 1000BASE-X/SGMII PCS and PMA Signals

Figure 60. 1000BASE-X/SGMII PCS Function and PMA Signals
  1. The clock enabler signals are present only in SGMII mode.
  2. The SERDES control signals are present in variations targeting devices with GX transceivers.
Table 97.  References
Interface Signal Section
Reset signals PCS Reset Signals
MII/GMII clocks and clock enablers MII/GMII Clocks and Clock Enablers
PCS control interface PCS Control Interface Signals
GMII signals GMII
MII signals MII
SGMII status signals SGMII Status Signals
1.25 Gbps serial signals 1.25 Gbps Serial Interface
Status LED signals Status LED Control Signals
SERDES control signals SERDES Control Signals
Transceiver Native PHY signal Transceiver Native PHY Signal