F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 8/16/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.2.1. Avalon Streaming Receive Interface

Figure 61. Receive Operation—MAC With Internal FIFO Buffers


Figure 62. Receive Operation—MAC Without Internal FIFO Buffers


Figure 63. Invalid Length Error During Receive Operation—MAC With Internal FIFO Buffer


Figure 64. Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers