F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents

4.1. Core Configuration

Table 11.  Core Configuration Parameters
Name Value Description
Core Variation
  • 10/100/1000 Mb Ethernet MAC
  • 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS
  • 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS 1 2
  • 1000BASE-X/SGMII PCS only
  • 1000BASE-X/SGMII 2XTBI PCS only 1 3
  • 1000 Mb Small MAC
  • 10/100 Mb Small MAC
Determines the primary blocks to include in the variation.
  • MII
  • GMII
Determines the Ethernet-side interface of the MAC block.
  • MII—The only option available for 10/100 Mb Small MAC core variations.
  • GMII—Available only for 1000 Mb Small MAC core variations.
  • MII/GMII—Available only for 10/100/1000 Mb Ethernet MAC core variations. If this is selected, media independent interface (MII) is used for the 10/100 interface, and gigabit media independent interface (GMII) for the gigabit interface.
Use clock enable for MAC On/Off Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/1000Mb Ethernet MAC and 1000Mb Small MAC core variations.
Use internal FIFO On/Off Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.
Note: To enable timestamping, turn off this option.
Number of ports 1, 4, 8, 12, 16, 20, and 24 Specifies the number of Ethernet ports supported by the IP. This parameter is enabled if the parameter Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers.
Transceiver type
  • None
  • LVDS I/O
  • FGT
This option is only available for variations that include the PCS block.
  • None—the PCS block does not include an integrated transceiver module. The PCS block implements a ten-bit interface (TBI) to an external SERDES chip.
  • LVDS I/O or FGT—the IP includes an integrated transceiver module to implement a 1.25 Gbps transceiver.
    • The FGT option is available only in the Intel FPGA devices with F-Tile transceivers.
1 This variation is only supported when you select Agilex™ 7 devices with F-Tile transceivers in the Quartus® Prime Pro Edition software.
2 Embedded PMA is included and is not optional. You must turn on Use internal FIFO option for this variation, except when timestamping is enabled.
3 Embedded PMA is excluded. You must manually connect the variant to the F-Tile or external PHY that supports 2XTBI interface.