F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/15/2024
Document Table of Contents Multiport MAC Receive Interface Signals

Table 60.  MAC Receive Interface Signals
Name Avalon Streaming Signal Type I/O Description
data_rx_valid_n valid O Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: data_rx_data_n, data_rx_sop_n, data_rx_eop_n, and data_rx_error_n.
data_rx_data_n[7:0] data O Receive data.
data_rx_sop_n startofpacket O Receive start of packet. Asserted when the first byte or word of a frame is driven on data_rx_data_n.
data_rx_eop_n endofpacket O Receive end of packet. Asserted when the last byte or word of frame data is driven on data_rx_data_n.
data_rx_ready_n ready I Receive application ready. Assert this signal on the rising edge of data_rx_clk_n when the user application is ready to receive data from the MAC function.

If the user application is not ready to receive data, the packet is dropped or truncated with an error.

data_rx_error_n[4:0] error O Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. For the description of each bit, refer to the description of bits 5 to 1 in MAC Receive Interface Signals . Bit 4 of this signal maps to bit 5 in the table and so forth.