Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.5.2. RX Statistics Registers

Table 28.  Receive Side Statistics Registers

Address

Name

Description

Access

0x900

CNTR_RX_FRAGMENTS_LO

Number of received frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x901

CNTR_RX_FRAGMENTS_HI

Number of received frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x902

CNTR_RX_JABBERS_LO

Number of received oversized frames reporting a CRC error (lower 32 bits)

RO

0x903

CNTR_RX_JABBERS_HI

Number of received oversized frames reporting a CRC error (upper 32 bits)

RO

0x904

CNTR_RX_FCS_LO

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error or rx_fcs_error output signal (lower 32 bits)

RO

0x905

CNTR_RX_FCS_HI

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error output signal (upper 32 bits)

RO

0x906

CNTR_RX_CRCERR_LO

Number of received frames with a frame of length at least 64, with CRC error (lower 32 bits)

RO

0x907

CNTR_RX_CRCERR_HI

Number of received frames with a frame of length at least 64, with CRC error (upper 32 bits)

RO

0x908

CNTR_RX_MCAST_DATA_ERR_LO

Number of errored multicast frames received, excluding control frames (lower 32 bits)

RO

0x909

CNTR_RX_MCAST_DATA_ERR_HI

Number of errored multicast frames received, excluding control frames (upper 32 bits)

RO

0x90A

CNTR_RX_BCAST_DATA_ERR_LO

Number of errored broadcast frames received, excluding control frames (lower 32 bits)

RO

0x90B

CNTR_RX_BCAST_DATA_ERR_HI

Number of errored broadcast frames received, excluding control frames (upper 32 bits)

RO

0x90C

CNTR_RX_UCAST_DATA_ERR_LO

Number of errored unicast frames received, excluding control frames (lower 32 bits)

RO

0x90D

CNTR_RX_UCAST_DATA_ERR_HI

Number of errored unicast frames received, excluding control frames (upper 32 bits)

RO

0x90E

CNTR_RX_MCAST_CTRL_ERR_LO

Number of errored multicast control frames received (lower 32 bits)

RO

0x90F

CNTR_RX_MCAST_CTRL_ERR_HI

Number of errored multicast control frames received (upper 32 bits)

RO

0x910

CNTR_RX_BCAST_CTRL_ERR_LO

Number of errored broadcast control frames received (lower 32 bits)

RO

0x911

CNTR_RX_BCAST_CTRL_ERR_HI

Number of errored broadcast control frames received (upper 32 bits)

RO

0x912

CNTR_RX_UCAST_CTRL_ERR_LO

Number of errored unicast control frames received (lower 32 bits)

RO

0x913

CNTR_RX_UCAST_CTRL_ERR_HI

Number of errored unicast control frames received (upper 32 bits)

RO

0x914

CNTR_RX_PAUSE_ERR_LO

Number of errored pause frames received (lower 32 bits)

RO

0x915

CNTR_RX_PAUSE_ERR_HI

Number of errored pause frames received (upper 32 bits)

RO

0x916

CNTR_RX_64B_LO

Number of 64-byte received frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x917

CNTR_RX_64B_HI

Number of 64-byte received frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x918

CNTR_RX_65to127B_LO

Number of received frames between 65–127 bytes (lower 32 bits)

RO

0x919

CNTR_RX_65to127B_HI

Number of received frames between 65–127 bytes (upper 32 bits)

RO

0x91A

CNTR_RX_128to255B_LO

Number of received frames between 128 –255 bytes (lower 32 bits)

RO

0x91B

CNTR_RX_128to255B_HI

Number of received frames between 128 –255 bytes (upper 32 bits)

RO

0x91C

CNTR_RX_256to511B_LO

Number of received frames between 256 –511 bytes (lower 32 bits)

RO

0x91D

CNTR_RX_256to511B_HI

Number of received frames between 256 –511 bytes (upper 32 bits)

RO

0x91E

CNTR_RX_512to1023B_LO

Number of received frames between 512–1023 bytes (lower 32 bits)

RO

0x91F

CNTR_RX_512to1023B_HI

Number of received frames between 512 –1023 bytes (upper 32 bits)

RO

0x920

CNTR_RX_1024to1518B_LO

Number of received frames between 1024–1518 bytes (lower 32 bits)

RO

0x921

CNTR_RX_1024to1518B_HI

Number of received frames between 1024–1518 bytes (upper 32 bits)

RO

0x922

CNTR_RX_1519toMAXB_LO

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (lower 32 bits)

RO

0x923

CNTR_RX_1519toMAXB_HI

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (upper 32 bits)

RO

0x924

CNTR_RX_OVERSIZE_LO

Number of oversized frames (frames with more bytes than the number specified in the MAX_RX_SIZE_CONFIG register) received (lower 32 bits)

RO

0x925

CNTR_RX_OVERSIZE_HI

Number of oversized frames (frames with more bytes than the number specified in the MAX_RX_SIZE_CONFIG register) received (upper 32 bits)

RO

0x926

CNTR_RX_MCAST_DATA_OK_LO

Number of valid multicast frames received, excluding control frames (lower 32 bits)

RO

0x927

CNTR_RX_MCAST_DATA_OK_HI

Number of valid multicast frames received, excluding control frames (upper 32 bits)

RO

0x928

CNTR_RX_BCAST_DATA_OK_LO

Number of valid broadcast frames received, excluding control frames (lower 32 bits)

RO

0x929

CNTR_RX_BCAST_DATA_OK_HI

Number of valid broadcast frames received, excluding control frames (upper 32 bits)

RO

0x92A

CNTR_RX_UCAST_DATA_OK_LO

Number of valid unicast frames received, excluding control frames (lower 32 bits)

RO

0x92B

CNTR_RX_UCAST_DATA_OK_HI

Number of valid unicast frames received, excluding control frames (upper 32 bits)

RO

0x92C

CNTR_RX_MCAST_CTRL_LO

Number of valid multicast frames received, excluding data frames (lower 32 bits)

RO

0x92D

CNTR_RX_MCAST_CTRL_HI

Number of valid multicast frames received, excluding data frames (upper 32 bits)

RO

0x92E

CNTR_RX_BCAST_CTRL_LO

Number of valid broadcast frames received, excluding data frames (lower 32 bits)

RO

0x92F

CNTR_RX_BCAST_CTRL_HI

Number of valid broadcast frames received, excluding data frames (upper 32 bits)

RO

0x930

CNTR_RX_UCAST_CTRL_LO

Number of valid unicast frames received, excluding data frames (lower 32 bits)

RO

0x931

CNTR_RX_UCAST_CTRL_HI

Number of valid unicast frames received, excluding data frames (upper 32 bits)

RO

0x932

CNTR_RX_PAUSE_LO

Number of received pause frames, with or without error (lower 32 bits)

RO

0x933

CNTR_RX_PAUSE_HI

Number of received pause frames, with or without error (upper 32 bits)

RO

0x934

CNTR_RX_RUNT_LO

Number of received runt packets (lower 32 bits)

A runt is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x935

CNTR_RX_RUNT_HI

Number of received runt packets (upper 32 bits)

A runt is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x936–0x944

Reserved

0x945

CNTR_RX_CONFIG

Bits[2:0]: Configuration of RX statistics counters:
  • Bit[2]: Shadow request (active high): When set to the value of 1, RX statistics collection is paused. The underlying counters continue to operate, but the readable values reflect a snapshot at the time the pause flag was activated. Write a 0 to release.
  • Bit[1]: Parity-error clear. When software sets this bit, the IP core clears the parity bit CNTR_RX_STATUS[0]. This bit (CNTR_RX_CONFIG[1]) is self-clearing.
  • Bit[0]: Software can set this bit to the value of 1 to reset all of the RX statistics registers at the same time. This bit is self-clearing.
Bits[31:3] are Reserved. 		RW
0x946 CNTR_RX_STATUS
  • Bit[1]: Indicates that the RX statistics registers are paused (while CNTR_RX_CONFIG[2] is asserted).
  • Bit[0]: Indicates the presence of at least one parity error in the RX statistics counters.
Bits [31:2] are Reserved. 		RO
0x947–0x95F

Reserved
0x960 RxPayloadOctetsOK_LO Number of received payload bytes in frames with no FCS, undersized, oversized, or payload length errors. If VLAN detection is turned off for the RX MAC (bit [1] of the RXMAC_CONTROL register at offset 0x50A has the value of 1), the IP core counts the VLAN header bytes (4 bytes for VLAN and 8 bytes for stacked VLAN) as payload bytes. This register is compliant with the requirements for aOctetsReceivedOK in section 5.2.2.1.14 of the IEEE Standard 802.3-2008. RO
0x961 RxPayloadOctetsOK_HI RO
0x962 RxFrameOctetsOK_LO Number of received bytes in frames with no FCS, undersized, oversized, or payload length errors. This register is compliant with the requirements for ifInOctets in RFC3635 (Managed Objects for Ethernet-like Interface Types) and RX etherStatsOctets in RFC2819 (Remote Network Monitoring Management Information Base (RMON)). RO
0x963 RxFrameOctetsOK_HI RO
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