Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

1.5.2. Compilation Checking

Intel® performs compilation testing on an extensive set of Low Latency 50G Ethernet IP core variations and designs to ensure the Quartus® Prime Pro Edition software places and routes the IP core ports correctly.