Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.1. PHY Registers

Table 22.  PHY RegistersThe global hard reset csr_rst_n resets all of these registers. The TX reset tx_rst_n and RX reset rx_rst_n signals do not reset these registers.
Addr Name Description Reset Access
0x300 REVID IP core PHY module revision ID. 0x0210 2017 RO
0x301 SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x302 PHY_NAME_0 First characters of IP core variation identifier string, "0050". The "00" is unprintable. 0x0000 3530 RO
0x303 PHY_NAME_1 Next characters of IP core variation identifier string, "00GE". The "00" is unprintable. 0x0000 4745 RO
0x304 PHY_NAME_2 Final characters of IP core variation identifier string, "0pcs". The "0" is unprintable. 0x0070 6373 RO
0x310 PHY_CONFIG PHY configuration registers. The following bit fields are defined:
  • Bit[0]: : eio_sys_rst. Full system reset (except registers). Set this bit to initiate the internal reset sequence.
  • Bit[1]: soft_txp_rst. TX soft reset.Resets TX PCS, MAC, and adapter.
  • Bit[2]: soft_rxp_rst. RX soft reset. Resets RX PCS, MAC, and adapter.
  • Bit[3]: Reserved.
  • Bit[4]: set_ref_lock. Directs the RX CDR PLL to lock to the reference clock.
  • Bit[5]: set_data_lock. Directs the RX CDR PLL to lock to data.
  • Bits[31:6]: Reserved.

26'hX_2'b0_1'bX_3'b0 2

RW
0x312 WORD_LOCK When asserted, indicates that the virtual channel has identified 66 bit block boundaries in the serial data stream. 30'hX4'b0 2 RO
0x313 EIO_SLOOP Serial PMA loopback. Setting a bit puts the corresponding transceiver in serial loopback mode. In serial loopback mode, the TX lane loops back to the RX lane on an internal loopback path. 30'hX2'b00 2 RW
0x314 EIO_FLAG_SEL Supports indirect addressing of individual FIFO flags in the PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the EIO_FLAGS register.

The value in the EIO_FLAG_SEL register directs the IP core to make available the following FIFO flag:

  • 3'b000: TX FIFO full
  • 3'b001: TX FIFO empty
  • 3b010: TX FIFO partially full
  • 3'b011: TX FIFO partially empty
  • 3b100: RX FIFO full
  • 3b101: RX FIFO empty
  • 3b110: RX FIFO partially full
  • 3b111: RX FIFO partially empty
29'hX3'b0 2 RW
0x315 EIO_FLAGS PCS indirect data. To read a FIFO flag, set the value in the EIO_FLAG_SEL register to indicate the flag you want to read. After you specify the flag in the EIO_FLAG_SEL register, each bit [n] in the EIO_FLAGS register has the value of that FIFO flag for the transceiver channel for lane [n]. 30'hX2'b0 2 RO
0x321 EIO_FREQ_LOCK Each asserted bit indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked. 30'hX2'b00 2 RO
0x322 PHY_CLK The following encodings are defined:
  • Bit[0]: Indicates if the TX PCS is ready
  • Bit [1]: Indicates if the TX PLL is locked.
  • Bit[2]: Indicates if the RX PLL is locked.
29'hX3'b00 2 RO
0x323 FRM_ERR

Each asserted bit indicates that the corresponding virtual lane has a frame error. You can read this register to determine if the IP core sustains a low number of frame errors, below the threshold to lose word lock. These bits are sticky, unless the IP core loses word lock. Write 1'b1 to the SCLR_FRM_ERR register to clear.

If the IP core loses word lock, it clears this register.

28'hX_4'b0 2 RO
0x324 SCLR_FRM_ERR Synchronous clear for FRM_ERR register. Write 1'b1 to this register to clear the FRM_ERR register and bit [1] of the LANE_DESKEWED register. A single bit clears all sticky framing errors.

This bit does not auto-clear. Write a 1'b0 to continue logging frame errors.

0x0 RW
0x325 EIO_RX_SOFT_PURGE_S

Set bit [0] to clear the RX FIFO for both physical lanes.

1'bX_1'b0 2

RO

RW
0x326 RX_PCS_FULLY_ALIGNED_S Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit[0]: RX PCS fully aligned status.
  • Bit[1]: RX PCS bit error rate status. A bit value of 1 indicates a bit error rate higher than 10-4 or there are at least 16 errors within 50 us. This bit value is only valid when the link fault generation is enabled.
31'hX1'b0 2 RO
0x328 AM_LOCK When asserted indicates that the physical channel has identified virtual lane alignment markers in the data stream. 28'hX_4'b0 2 RO
0x329 LANE_DESKEWED
The following encodings are defined:
  • Bit [0]: Indicates all lanes are deskewed.
  • Bit [1]: When asserted indicates a change in lanes deskewed status. To clear this sticky bit, write 1'b1 to the corresponding bit of the SCLR_FRM_ERR register. This is a latched signal.
30'hX2'b00 2 RO
0x330 PCS_VLANE The following encodings are defined:
  • Bit [1:0]: First virtual index for physical lane 0.
  • Bit [3:2]: Second virtual index for physical lane 0.
  • Bit [5:4]: First virtual index for physical lane 1.
  • Bit [7:6]: Second virtual index for physical lane 1.
24'bX8'b0 2 RO
0x331 PHY_RX_DELAY Test and debug feature to test deskew. Allows you to insert a programmable skew on one physical channel.
  • Bit[0]: Allows you to you to shift 33 bits for incoming stream in physical channel 0, effectively inserting sew on two of the virtual lanes.
  • Bit[5:1]: Allows you to insert a 1-32 word delay on the two virtual channels arriving on physical lane 0. To use bits[5;1], you must set an RX PCS dynamic parameter that is not exposed at the top level (DYNAMIC_SKEW).
26'hX_6'b0 RW
0x340 KHZ_REF The register indicates the value of reference clock frequency. Apply the following definition for the frequency value:

[(Register value 3 * clk_status)/10] KHZ

0x0000 0000 RO
0x341 KHZ_RX The register indicates the value of RX clock (clk_rxmac) frequency. Apply the following definition for the frequency value:

[(Register value 3 * clk_status)/10] KHZ

0x0000 0000 RO
0x342 KHZ_TX The register indicates the value of TX clock (clk_txmac) frequency. Apply the following definition for the frequency value:

[(Register value 3 * clk_status)/10] KHZ

0x0000 0000 RO
2 X means "Don't Care".
3 Register value convert in decimal.
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