Low Latency 50G Ethernet Intel FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683675
Date 12/14/2020
Public
Document Table of Contents

5.3. Transceivers

The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. For the Low Latency 50G Ethernet IP core, you can use the same ATX PLL for both transceivers.

Table 15.  Transceiver Signals
Signal Direction Description
tx_serial[1:0] Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[1:0] Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz.
tx_serial_clk Input High speed serial clock driven by the ATX PLL. The frequency of this clock is 12.890625 GHz.
tx_pll_locked Input Lock signal from ATX PLL. Indicates all ATX PLL(s) are locked.