Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

4.3.3. IP Core Malformed Packet Handling

While receiving an incoming packet from the Ethernet link, the Low Latency 50G Ethernet IP core expects to detect a terminate character at the end of the packet. When it detects an expected terminate character, the IP core generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control character when it expects a terminate character.

If the Low Latency 50G Ethernet IP core detects an Error character, a Start character, an IDLE character, or any other non-terminate control character, when it expects a terminate character, it performs the following actions:

  • Generates an EOP.
  • Asserts a malformed packet error (l1_rx_error[0] l2_rx_error[0]).
  • Asserts an FCS error (l1_rx_error[1] l2_rx_error[1]).

If the IP core subsequently detects a terminate character, it does not generate another EOP indication.

When the IP core receives a packet that contains an error, the IP core identifies it as a malformed packet.