Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

5.5. Avalon® Memory-Mapped Management Interface

You access control and status registers using an Avalon® memory-mapped management interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the csr_rst_n signal.

Asserting the csr_rst_n signal resets all control and status registers except the statistics registers; while this reset is in process, the Avalon® memory-mapped management interface does not respond.

Table 17.   Avalon® Memory-Mapped Management Interface All status_* signals are synchronous to clk_status signal.
Signal Direction Description
clk_status Input The clock that drives the control and status registers. The frequency of this clock is 100 MHz.
reset_status Input Connect this signal to 1'b0. This signal remains visible as a top-level signal for backward compatibility.
status_addr[15:0] Input Drives the Avalon® memory-mapped register address.
status_read Input When asserted, specifies a read request.
status_write Input When asserted, specifies a write request.
status_readdata[31:0] Output Drives read data. Valid when status_readdata_valid is asserted.
status_readdata_valid Output When asserted, indicates that status_read_data[31:0] is valid.
status_writedata[31:0] Input Drives the write data. The packet can end at any byte position. The empty bytes are the low-order bytes.
status_waitrequest Output Indicates that the control and status interface is not ready to complete the transaction. status_waitrequest is only used for read transactions.