Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

1. About the Low Latency 50G Ethernet IP Core

Updated for:
Intel® Quartus® Prime Design Suite 20.4
IP Version 1.0.0

The Low Latency 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Schedule 3 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. This specification enables high-performance, cost-efficient, and scalable interconnects for data center networks with server to top-of-rack links that are able to utilize the 50G dual-lane technology.

The IP core provides standard Media Access Control (MAC) and Physical Coding Sublayer (PCS), and Physical Medium Attachment (PMA) functions shown in the following block diagram. The PHY comprises the PCS and PMA based on Clause 82 of IEEE Std 802.3, operating at a data rate of 50 Gb/s.

Figure 1.  Low Latency 50G Ethernet IP Block Diagram