Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 Link Training Config Register 2 Fields 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.6.16. Link Training Config Register 2

Provides CSRs for the following link training features:
  • Restart Link Training on Lane 0
  • Restart Link Training on Lane 1
  • Restart Link Training on Lane 2
  • Restart Link Training on Lane 3
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 0
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 1
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 2
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 3
  • Updated Local TX EQ Override Settings ready to be sent for Lane 0
  • Updated Local TX EQ Override Settings ready to be sent for Lane 1
  • Updated Local TX EQ Override Settings ready to be sent for Lane 2
  • Updated Local TX EQ Override Settings ready to be sent for Lane 3

Offset: 0xD1

Access: RW

Link Training Config Register 2 Fields

Bit Name Description Access Reset
11 updated_local_coef_ln3 Updated Local TX EQ Override Settings ready to be set for Lane 3

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 3

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
10 updated_local_coef_ln2 Updated Local TX EQ Override Settings ready to be set for Lane 2

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 2

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR

RW 0x0
9 updated_local_coef_ln1 Updated Local TX EQ Override Settings ready to be set for Lane 1

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 1

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
8 updated_local_coef_ln0 Updated Local TX EQ Override Settings ready to be set for Lane 0

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 0

0: Normal operation

Valid only when ovride_local_coef_enable=1

Takes values from corresponding TX EQ Override CSR

RW 0x0
7 updated_lp_coef_ln3 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 3

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 3

0: Normal operation

Valid only when ovride_lp_coef_enable=1

Takes values from corresponding TX EQ Override CSR.

RW 0x0
6 updated_lp_coef_ln2 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 2

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 2

0: Normal operation

Valid only when ovride_lp_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
5 updated_lp_coef_ln1 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 1

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 1

0: Normal operation

Valid only when ovride_lp_coef_enable=1

Takes values from corresponding TX EQ Override CSR.

RW 0x0
4 updated_lp_coef_ln0 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 0

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 0

0: Normal operation

Valid only when ovride_lp_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
3 restart_link_training_ln3 Restart Link Training on lane 3

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
2 restart_link_training_ln2 Restart Link Training on lane 2

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
1 restart_link_training_ln1 Restart Link Training on lane 1

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
0 restart_link_training_ln0 Restart Link Training on lane 0

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
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