Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 Link Training Config Register 1 Fields 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.6.15. Link Training Config Register 1

Provides CSRs for the following link training features:
  • Enable Link Training
  • Disable Max Wait Timer
  • Disable Initialize PMA on Max Wait Timeout
  • Enable Link Partner TX EQ Coefficient Override
  • Enable Local TX EQ Coefficient Override
  • Enable Manual RX Settings for Link Training
  • Manual CTLE AC set by IP during Link Training
  • Manual CTLE DC set by IP during Link Training
  • Manual VGA set by IP during Link Training

Offset: 0xD0

Access: RW

Link Training Config Register 1 Fields

Bit Name Description Access Reset
31:28 lt_rx_vga Manual VGA set by IP during Link Training

The IP multiply the value set in this field by 2, e.g. if the value is 7, VGA is set to 14.

This file is only valid when lt_rx_manual_mode is set to 1.

RW 0x0
27:23 lt_rx_clte_dc Manual CTLE DC set by IP during Link Training

The IP multiply the value set in this field by 2, e.g. if the value is 7, the CTLE DC is set to 14.

This file is only valid when lt_rx_manual_mode is set to 1.

RW 0x0
22:20 lt_rx_clte_ac Manual CTLE AC set by IP during Link Training

The IP multiply the value set in this field by 2, e.g. if the value is 7, the CTLE AC is set to 14.

This file is only valid when lt_rx_manual_mode is set to 1.

RW 0x0
19 lt_rx_manual_mode Enable Manual RX Settings for Link Training

1: Link training use manual RX settings from this register.

0: Link training automatically adapt RX settings.

The default value is 1 in simulation and 0 in synthesis.

RW 0x0
17 ovride_local_coef_enable Enable Local TX EQ Coefficient Override

1: Override the Local device TX EQ coefficients

0: Let the Link Partner decide the local TX EQ coefficients

RW 0x0
16 ovride_lp_coef_enable Enable Link Partner Coefficient Override

1: Override the Link Partner EQ coefficients

0: Use the Link Training logic to decide the Link Partner TX EQ coefficients

When this field is set to 1, user logic must decide the Link Partner TX EQ coefficient values.

RW 0x0
15 disable_initialize_pma_on_max_wait_timeout Disable initialize PMA on max_wait_timeout

1: Don't initialize TX EQ to INIT values upon entry into the Training_Failure state of link training

0: Set TX EQ to INIT values upon entry into the Training_Failure state of link training (default)

RW 0x0
14:12 fine_tune_rounds Number of Fine Tuning Rounds to perform:
  • May need to be reduced for interoperation with slower Link Partners
  • Defaults to 0 in simulation, 0 in synthesis
 RW 0x0
11:8 main_pre_steps Number of Main Tap Steps to create headroom for Preset Condition
  • When using Start from Preset setting in 0xd0[7], the headroom must be created by decrementing the Main Tap before TX training can continue.
  • Defaults to 0 in simulation, 0 in synthesis
 RW 0x0
7 lt_start_init Start from Initialize Condition on Link Partner TX Taps
  • 1: Start from Initialize Condition
  • 0: Start from Preset Condition
Initialize condition may result in more stable Link Training on challenging links. Defaults to 1 in simulation, 0 in synthesis. 		RW 0x1
6 dis_post_fine_tune Disable Fine Tuning on Link Partner TX Post-Tap
  • 1: Disable Post-Tap Fine-Tuning
  • 0: Enable Post-Tap Fine-Tuning(default)
  • Defaults to 1 in simulation, 0 in synthesis
 RW 0x1
5 dis_pre_fine_tune Disable Fine Tuning on Link Partner TX Pre-Tap
  • 1: Disable Pre-Tap Fine-Tuning
  • 0: Enable Pre-Tap Fine-Tuning(default)
  • Defaults to 1 in simulation, 0 in synthesis
 RW 0x1
4 dis_main_train Disable Training Link Partner TX Main-Tap
  • 1: Disable Main-Tap Training
  • 0: Enable Main-Tap Training(default)
If Start from Preset is selected in 0xd0[7], The Link Partner Main Tap is still be adjusted for headroom based on 0xd0[11:8].

Defaults to 1 in simulation, 0 in synthesis

 RW 0x1
3 dis_post_train Disable Training Link Partner TX Post-Tap
  • 1: Disable Post-Tap Training
  • 0: Enable Post-Tap Training(default)
Defaults to 1 in simulation, 0 in synthesis 		RW 0x1
2 dis_pre_train Disable Training Link Partner TX Pre-Tap
  • 1: Disable Pre-Tap Training
  • 0: Enable Pre-Tap Training(default)
Defaults to 1 in simulation, 0 in synthesis 		RW 0x1
1 dis_max_wait_tmr Disable Max Wait Timer
  • 1: Disable Max Wait Timer
  • 0: Use Max Wait Timer (default)

When the Max Wait Timer is disabled, the Link Training does not fail, but the IP can potentially stay in the LT state indefinitely.

Intel recommends to enable this bit when using Link Training without Auto negotiation.

When this bit is enabled, Link Fail Timeout is ignored during Link Training

RW 0x0
0 enable_link_training Enable Link Training

1: Enable link training

0: Disable link training

RW 0x1
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